1. Field of the Invention
The invention relates to a semiconductor memory device, such as a static random access memory (SRAM) device or a dynamic random access memory (DRAM) device. More specifically, the present invention relates to a semiconductor memory device that can be preset to a particular value without requiring an initial write operation for each cell of a memory cell array.
2. Description of the Related Art
Semiconductor memory devices, which offer a large storage capacity in a single chip at a reasonable cost, are widely used in electronic systems, such as computer, communication and consumer equipment. Recent advancements in semiconductor technology, most notably in the art of providing a complete system on a single chip, have made it possible to embed a memory device in an integrated circuit that functions as a complete system with a large data storage capability. The embedded technology further widens the field of applications for semiconductor memory devices, and can provide flexible granularity for each specific application.
Many applications, such as digital video compression, require a random access memory (RAM) array to be preset to a particular value. That is, each cell in the RAM array, such as an SRAM or DRAM array, is set to a logic 0 or a logic 1 by a write command. If the cells are preset sequentially by a series of write commands, the process can be very time consuming, especially for high density memory cell arrays. On the other hand, if all the cells in a high density memory array are simultaneously preset, such as by turning on all the address lines of the memory array and writing a logic 0 or a logic 1 therein, the resultant current surge can generate a significant amount of power noise on the power supply rail. This power noise may cause significant malfunctions in both digital and analog components, as well as inadvertent data alterations in various memory components of the system. Since industry trends require continuing increases in the number of memory bits per chip, thus increasing the density requirements of semiconductor memory arrays, it is incumbent upon the chip designer to develop presetting techniques for high density memory arrays which are not excessively time consuming, and which do not cause the undesirable current surge problem noted above.
FIG. 1 shows a typical prior art RAM structure, configured with p words and q bits. Each word represents an access unit. In this example, q parallel bits are simultaneously accessed in response to a read or write operation. The RAM device comprises an address decoder 1 and an array 2 having an input/output (I/O) gateway 3. The array 2 has p by q entries. A single bit, e.g. BITO 20, comprises p cells of different addresses and companion devices on internal data lines for facilitating data access. Address decoder 1, in response to an address bus, decodes address lines for the p words. I/O gateway 3 has q cells, each of which is associated with a single bit, and provides a data path for writing data from a data bus to array 2, and also for reading data from array 2 to the data bus.
FIG. 2 shows address decoder 1 and a single bit 20 of an SRAM array according to FIG. 1 in greater detail. The array cells of single bit 20 are organized into m rows and n columns, where m.times.n=p. Address decoder 1 is divided into a row address decoder 11 and a column address decoder 12. Row address decoder 11 decodes m row select lines X0, X1, . . . Xm-1 for the m rows. Column address decoder 12 decodes n column select lines Y0, Y1, . . . Yn-1 for the n columns. Array cells of a same row share, and are cascaded by, a row select line e.g. X0. Array cells of a same column are shunted along a pair of data lines, e.g. C0 and CN0. The data line pairs of the n columns are combined into a pair of bit lines, B and BN, by n switches, each of which corresponds to one of the n columns. Each column select line Y0, Y1, . . . Yn-1 outputted from column address decoder 12 controls the turning on or turning off of the corresponding switch. Each data line pair C0, CN0; C1, CN1; . . . Cn-1, CNn-1 is charged by a pre-charge cell, e.g. 201, which equalizes both data lines to a certain voltage level when no access event occurs. A pre-charge cell 202 performs the same voltage equalizing function on the pair of bit lines B, BN. An I/O circuit 203, in response to a write control signal, passes data on the data bus to the bit lines B, BN. In response to a read control signal, I/O circuit 203 senses the voltage difference between the bit lines B, BN, and outputs a definite logic state to the data bus.
Each array cell of the SRAM array is typically a six-transistor or a four-transistor memory cell within a CMOS circuit. Each switch is typically an NMOS pass transistor. The pairs of data lines Cj, CNj (where j=0 to n-1) and the pair of bit lines B, BN are complementary. I/O circuit 203 typically contains an input buffer and a sense amplifier operating exclusively in respective write and read access cycles. The pre-charge cells, e.g. 201 and 202, and the I/O circuit 203 form parts of the I/O gateway 3.
FIG. 3 shows address decoder 1 and a single bit 20a of a DRAM array according to FIG. 1 in greater detail. The array cells of single bit 20a are also organized into m rows and n columns, where m.times.n=p. Like the address decoder 1 of FIG. 2, the row address decoder 11 decodes m row select lines X0, X1, . . . Xm-1 for the m rows, whereas the column address decoder 12 decodes n column select lines Y0, Y1, . . . Yn-1 for the n columns. Array cells of a same row share, and are cascaded by, a row select line e.g. X0. Unlike the single bit 20 of FIG. 2, array cells of a same column are connected to only one of a pair of data lines, e.g. C0 and CN0. The data line pairs of the n columns are combined into a pair of bit lines, B and BN, by n switches, each of which corresponds to one of the n columns. Each column select line Y0, Y1, . . . Yn-1 outputted from column address decoder 12 controls the turning on or turning off of the corresponding switch. Like the single bit 20 of FIG. 2, each data line pair C0, CN0; C1, CN1; . . . Cn-1, CNn-1 is charged by a pre-charge cell, e.g. 201a, which equalizes both data lines to a certain voltage level when no access event occurs. Each data line pair incorporates a sense amplifier, e.g. 204, to sense the voltage difference during a read access cycle. I/O circuit 203a, in response to a write control signal, passes data on the data bus to bit lines B, BN. In response to a read control signal, I/O circuit 203a senses the voltage difference between the bit lines B, BN, and outputs a definite logic state to the data bus.
Each array cell of the DRAM array is typically a single-transistor DRAM cell that includes a select transistor and a capacitor for charge storage. Each switch is typically an NMOS pass transistor. The pairs of data lines Cj, CNj (where j=0 to n-1) and pair of bit lines B, BN are complementary. I/O circuit 203a typically contains an input buffer and a sense amplifier operating exclusively in respective write and read access cycles.
In FIGS. 2 and 3, in the special case where n=1, the array cells are constructed as p rows by one column, and the switches and the column address decoder 12 can be omitted. The data lines Cj, CNj represent exactly the bit lines B, BN of the array cells such that only one sense amplifier is needed to detect the output state of the bit lines B, BN.
As stated above, presetting each array cell sequentially can be very time consuming, whereas simultaneous presetting or simultaneous resetting or clearing of the array cells may generate current surge noise problems.
One prior art technique to overcome the current surge problem when simultaneously resetting or clearing multi-byte data is described in U.S. Pat. No. 5,212,663. In this patent, an array of flag bits is added to the memory cell array of an SRAM device such that each word line of the memory cell array is associated with a corresponding flag bit. The flag bits are simultaneously reset to a logic "1" state at the instant power is restored to the SRAM device. A reset control circuit is used to create a logical relationship between the flag bits and the data in the memory cell array so that the resettable SRAM device presents a logic "0" output for all bits of the selected data when the corresponding flag bit is set to the logic "1" state, irrespective of the actual content of the memory cells. Thus, the need to reset all of the memory cells in the memory array is eliminated through the use of the flag bits.
This prior art technique, however, is only directed to the resetting of the entire SRAM array and does not allow for presetting of the SRAM array to a particular value without an initial write operation to each cell of the SRAM array.
DRAM cells are known to leak off stored charges to eventually change into an equivalent low level state unless a refresh operation is conducted periodically. However, allowing the DRAM cells to leak off stored charges does not result in presetting of the DRAM cells to a logic high level state.